ASIC Physical Design R&D Manager

Job Title

ASIC Physical Design R&D Manager

Role Summary

Lead a physical design R&D team responsible for digital and mixed-signal ASIC implementation, ensuring timing, power, and area targets while coordinating across RTL, DFT, packaging, and systems teams.

Own the technical strategy, execution, and tapeout readiness for next-generation ASIC products.

Experience Level

Senior — requires approximately 7+ years in digital ASIC physical design and 5+ years of program/project management experience.

Responsibilities

Primary duties include technical leadership, team development, and overseeing physical implementation and tapeout processes.

• Define and drive physical design strategy: floorplanning, power architecture, and implementation trade-offs to meet PPA targets.
• Lead, mentor, and develop a high-performing physical design team and set expectations for technical rigor and execution.
• Oversee physical implementation for digital, mixed-signal, and third-party IP, including place & route, timing closure, and power closure.
• Coordinate handoffs with RTL/design, DFT/test, packaging, and systems teams and resolve issues rapidly.
• Continuously improve physical-design flows, automation, methodology, and best practices for quality and predictability.
• Lead physical verification and signoff processes with clear criteria for tape release.
• Act as primary interface with foundries regarding PDKs and tapeout execution.
• Manage project execution, resourcing, scheduling, and risk mitigation across the physical-design lifecycle.

Requirements

Must-have skills and experience for this role.

• 7+ years of experience in digital ASIC physical design with successful tape releases.
• 5+ years of program/project management experience coordinating cross-functional teams.
• Proven leadership and people-management experience, including mentoring engineers.
• Expertise in physical implementation and layout methodology, including timing closure and optimization.
• Knowledge of DFT methodologies and their impact on physical design.
• Strong fundamentals in ASIC design concepts and understanding of CMOS/BiCMOS processes.
• Ability to evaluate and execute PPA trade-offs and make sound technical judgments under pressure.
• Effective communicator with demonstrated cross-functional influence and problem-solving skills.

Education Requirements

B.S. or M.S. in Electrical Engineering or Computer Engineering, or equivalent practical experience.

About the Company

Company: Keysight Technologies

Headquarters: Santa Rosa, CA, USA

Keysight Technologies is a global leader in electronic design, simulation, and test and measurement solutions for communications, automotive, aerospace, semiconductor, and industrial markets. The company provides instruments, software, and services to accelerate product development and manufacturing, employing approximately 15,000 people worldwide.