Job Title
ASIC Physical Design Engineer
Role Summary
Work on physical implementation of large-scale ASICs (100β400M gates) across advanced process nodes (7nmβ2nm). Part of a physical design team responsible for RTL-to-GDS flows, timing closure, and physical verification for high-performance integrated circuits.
Experience Level
Mid-level (requires a minimum of 5 years of relevant physical design experience).
Responsibilities
Primary responsibilities include end-to-end physical implementation and verification of ASIC designs.
- Use commercial and in-house EDA tools (Synopsys, Cadence, Siemens) for physical design and implementation.
- Execute full RTL/Gates-to-GDS flow: placement, clock tree synthesis, routing, and timing closure.
- Perform physical verification and formal verification; resolve LVS/DRC and signoff issues.
- Analyze and debug timing violations across hierarchical blocks and full-chip designs.
- Target designs in advanced process technologies (7nm, 5nm, 3nm, 2nm) with high gate counts.
- Develop and maintain automation and scripts in UNIX/Linux environments (tcl, bash).
Requirements
Minimum technical skills and experience required or preferred.
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Must-have: Minimum 5 years experience in ASIC physical design focused on placement, CTS, routing, and timing closure.
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Must-have: Proficiency with EDA tool flows and physical verification methodologies.
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Must-have: Strong UNIX/Linux and scripting skills (tcl, bash).
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Nice-to-have: Familiarity with front-end design and synthesis.
Education Requirements
Bachelor's, Master's or PhD in Electrical Engineering, Electronics Engineering, Computer Engineering, or a closely related technical field.
About the Company
Company: Broadcom
Headquarters: Irvine, California, United States
Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.

Date Posted: 2026-06-24