ASIC Floorplan Design Engineer
Responsible for developing and optimizing chip floorplans during early ASIC/GPU/SoC development. Works with architects, design leads, physical design and package teams to influence area, interconnect, timing and routing decisions.
Role focuses on floorplan creation, congestion and timing-resolution strategies, and tool/flow improvements to optimize area and execution speed.
Mid-level; typically requires 3+ years of relevant ASIC/VLSI experience.
Core responsibilities include early floorplan development, cross-team coordination, and tooling/automation to improve physical design outcomes.
Must-have technical skills and experience.
Master's degree in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent practical work experience.
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
