ASIC Engineering Intern, Design Verification (Silicon Engineering)

Job Title

ASIC Engineering Intern, Design Verification (Silicon Engineering)

Role Summary

Join the Silicon Accelerators verification team to verify digital IP for computer vision and image signal processing in AR hardware. You will write testbenches and tests, run regressions, debug RTL and testbench issues, and work with design and methodology engineers.

This is a production-level engineering internship intended to provide practical design verification experience in preparation for a full-time Design Verification role.

Experience Level

Entry-level internship for current graduate students (Master's). Designed for candidates with practical Verilog/SystemVerilog and scripting experience; prior verification exposure is beneficial.

Responsibilities

Primary day-to-day responsibilities include:

• Write SystemVerilog testbenches and tests for digital IP in vision and image-processing pipelines.
• Build and extend UVM-based verification components (sequences, drivers, monitors, scoreboards) under senior guidance.
• Develop verification test plans: stimulus, checks, and coverage goals.
• Run simulations, debug failures, and isolate bugs to RTL or test environment.
• Track functional and code coverage; write directed and constrained-random tests to close gaps.
• Write Python scripts to automate regressions, triage results, and improve workflows.
• Collaborate with design and methodology engineers and present results in team reviews.

Requirements

Must-have and preferred technical skills and constraints.

Must-have

• Experience with Verilog or SystemVerilog from coursework, labs, or projects.
• Programming experience in an object-oriented language (examples: SystemVerilog classes, C++, Python, Java).
• Scripting experience in Python for automation and regression tasks.
• Ability to obtain and maintain work authorization in the country of employment at time of hire.

Nice-to-have

• Exposure to UVM or other class-based verification methodologies.
• Familiarity with constrained-random stimulus, functional coverage, assertions (SVA), and scoreboarding.
• Hands-on experience with RTL simulators (e.g., VCS, Xcelium, Questa, Verilator) and waveform debugging.
• Completed digital design or verification projects (processor, memory controller, bus/interface, FPGA designs).
• Strong debugging instincts, curiosity, and clear communication skills.

Education Requirements

Currently has, or is in the process of obtaining, a Master's degree in Electrical Engineering, Computer Engineering, or a related technical field. The posting specifies intent to return to a full-time degree program after completion of the internship. Relevant coursework or projects include digital logic design (logic gates, flip-flops, FSMs, timing, clock domains), image processing, computer vision, signal processing, or AI/ML hardware acceleration.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.