ASIC Engineer, Performance Architecture and Modeling (University Grad)
Meta PlatformsJob Title
ASIC Engineer, Performance Architecture and Modeling (University Grad)
Role Summary
Join Meta's Silicon Engineering team to own performance architecture, pre-silicon modeling, and microarchitectural exploration for custom infrastructure ASICs. The role focuses on building and validating performance models and workloads that inform silicon architecture, guide design trade-offs, and ensure throughput, latency, and efficiency targets for data center and AI workloads.
Experience Level
Entry-level / University graduate. Candidates are expected to be recent graduates or completing a relevant degree prior to joining (0–3 years of experience).
Responsibilities
Key responsibilities include modeling, analysis, and cross-functional collaboration to drive architecture decisions and performance validation.
- Drive microarchitectural exploration and trade-off analysis across compute, memory, interconnect, and I/O.
- Define and own performance modeling strategy, including cycle-accurate and transaction-level simulators.
- Develop and maintain C++ models of chip IPs and subsystems for architecture exploration and software development.
- Create low-level workloads and kernels for ML training and inference; establish benchmarking frameworks and bottleneck identification methods.
- Collaborate with architecture, RTL, physical design, software, and systems teams to translate performance goals into implementable specs.
- Lead technical reviews, present modeling results and architectural recommendations to engineering leadership.
- Define long-term tooling and simulation infrastructure roadmaps; mentor peers on modeling and analysis practices.
- Perform model-to-hardware correlation and root-cause analysis to resolve performance gaps.
Requirements
Must-have technical skills and domain experience.
- Proficiency in C++ and Python for simulation models, automation, and analysis.
- Experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs.
- Experience analyzing data center, AI accelerator, or HPC workloads on custom silicon.
- Experience developing cycle-accurate or transaction-level performance models (C++/SystemC) for complex digital systems.
- Experience defining microarchitectural specifications and driving alignment across architecture, RTL, and physical design teams.
- Familiarity with assembly-level programming and compiler technologies.
Preferred / Nice-to-have qualifications:
- Python-based automation for simulation orchestration, regression testing, and performance data analysis.
- Knowledge of AI numerics, data types, and precision/accuracy trade-offs.
- Experience with CUDA or equivalent GPU programming and optimizing compute kernels.
- Familiarity with post-silicon validation, model-to-hardware correlation, and hardware description languages (SystemVerilog, VHDL).
- Experience with high-level synthesis, PPA trade-off analysis, or scaling performance modeling infrastructure for hyperscale ASICs.
Education Requirements
Required: Bachelor's, Master's, or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a closely related technical field, or equivalent practical experience. Candidates may be in the process of completing their degree but the degree must be finished prior to joining Meta.
About the Company
Company: Meta Platforms
Headquarters: Menlo Park, California, United States
American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.
