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ASIC Engineer, Design Verification

Meta Platforms
July 02, 2026
Full-time
On-site
Bengaluru, Karnataka, India
Verification Jobs, Level - Entry or Early Career

Job Title

ASIC Engineer, Design Verification

Role Summary

Join Meta's Infrastructure organization to verify IP and SoC designs for data-center applications. The role focuses on creating verification plans, building UVM-based testbenches, and driving verification closure using simulation, formal, and emulation techniques.

This position partners with design, emulation, software, and post-silicon teams to achieve first-pass silicon success for data-center ASICs.

Experience Level

Entry-level β€” requires approximately 2+ years of relevant design verification experience.

Responsibilities

Primary responsibilities include planning and executing verification activities for IP, sub-systems, or SoC blocks.

  • Define and implement IP/SoC verification plans and metrics.
  • Design and build UVM-based verification testbenches and functional tests.
  • Drive verification to closure using test plans, functional and code coverage targets.
  • Debug and root-cause functional failures in collaboration with design teams.
  • Collaborate with cross-functional teams (Design, Model, Emulation, Silicon validation) to ensure design quality.
  • Improve verification flows and infrastructure using current methodologies and tools.

Requirements

Key must-have technical skills and experience; preferred items are listed as nice-to-have.

  • Must-have: 2+ years of hands-on experience with SystemVerilog/UVM and/or C/C++ based verification.
  • Must-have: Experience with SystemVerilog Assertions, Formal methods, and/or Emulation as applied to verification.
  • Must-have: Experience using EDA/verification tools and scripting (Python, TCL, Perl, Shell) to build verification flows and tools.
  • Must-have: Experience architecting and implementing verification infrastructure and executing full verification cycles.
  • Nice-to-have: IP/sub-system/SoC level verification experience and building UVM environments from scratch.
  • Nice-to-have: Experience with ASIC development lifecycles, ARM or RISC-V sub-systems, and data-center application domains (video, AI/ML, networking).
  • Nice-to-have: Verification experience with high-speed interfaces (AMBA, PCIe, DDR, Ethernet) and familiarity with revision control systems (Mercurial, Git, SVN).

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field; or equivalent practical experience.


About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.

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Date Posted: 2026-07-02