ASIC Engineer, Design Verification

Job Title

ASIC Engineer, Design Verification

Role Summary

Join the Infrastructure organization to verify IP and SoC designs for Meta's data-center applications. The role focuses on planning and executing verification activities, developing UVM-based testbenches, and using simulation, formal, and emulation to achieve verification closure.

You will work with cross-functional teams including RTL design, emulation, modeling, and post-silicon validation to drive first-pass silicon quality.

Experience Level

Mid-level. The posting requests 6+ years of hands-on ASIC design verification experience.

Responsibilities

Primary responsibilities include defining verification plans, implementing test environments, and driving closure against verification metrics.

• Define and implement IP/SoC verification plans and test strategies.
• Develop UVM/SystemVerilog-based testbenches and functional tests from the verification plan.
• Drive verification to closure using metrics such as functional and code coverage.
• Debug and root-cause functional failures; collaborate with RTL design teams to resolve issues.
• Integrate and coordinate with emulation, model, and silicon validation teams.
• Adopt and improve verification methodologies, tools, and flows.

Requirements

Must-have:

• 6+ years of hands-on ASIC design verification experience.
• Proficiency in Verilog, SystemVerilog, and C/C++ for verification and UVM methodology.
• Experience in IP/sub-system and SoC level verification using SystemVerilog UVM/OVM.
• Experience with EDA tools and scripting (Python, TCL, Perl, Shell) to build verification flows and utilities.
• Experience architecting and implementing verification infrastructure and executing full verification cycles.

Nice-to-have:

• Verification experience with ARM or RISC-V sub-systems or SoCs.
• Track record of first-pass silicon success in ASIC projects.
• Experience with data-center domain designs (Video, AI/ML, Networking).
• Experience with high-speed interface verification (PCIe, DDR, Ethernet).
• Familiarity with revision control systems (Mercurial, Git, SVN) and building UVM environments from scratch.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field is listed; the posting also accepts equivalent practical experience.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.