ASIC Digital Verification Principal Engineer
SynopsysJob Title
ASIC Digital Verification Principal Engineer
Role Summary
The role involves designing and implementing verification environments to ensure the correctness of Interface IP protocols as part of a highly skilled verification team focused on delivering cutting-edge solutions.
Experience Level
Senior level, with extensive experience in ASIC digital verification.
Responsibilities
Key responsibilities include:
- Designing and implementing verification environments for Interface IP protocols.
- Creating and executing test plans to verify complex ASIC designs.
- Developing and maintaining verification IP and testbenches using SystemVerilog and UVM.
- Collaborating with design and architecture teams to identify and fix bugs.
- Performing functional coverage analysis and driving coverage closure.
- Mentoring junior verification engineers in best practices.
Requirements
Must-have qualifications include:
- Extensive experience in ASIC digital verification, especially with Interface IP protocols (e.g., PCIe, CXL, DDR, Ethernet).
- Proficiency in SystemVerilog and UVM methodologies.
- Strong understanding of digital design and verification concepts.
- Experience with simulation tools like VCS, ModelSim, or similar.
- Excellent problem-solving skills and attention to detail.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
