ASIC Digital Verification Principal Engineer

Role Overview

The ASIC Digital Verification Principal Engineer role involves working on challenging verification tasks within the verification team. This position requires a deep understanding of verification methodologies and the ability to mentor junior engineers while ensuring high-quality design output.

Position Summary

The candidate will be responsible for managing complex ASIC verification tasks, focusing on Interface IP protocols while utilizing advanced tools and techniques to ensure the specifications are met. You will collaborate with cross-functional teams for a comprehensive and cohesive approach to verification.

Experience Level

This role is suited for experienced professionals in ASIC digital verification, particularly those with a strong backend in Interface IP protocol verification and solid expertise with tools like SystemVerilog and UVM.

Your Responsibilities

• Design and implement verification environments for Interface IP protocols.
• Create and execute test plans to assess complex ASIC designs thoroughly.
• Develop and maintain verification IP and testbenches using SystemVerilog and UVM.
• Collaborate with design teams to identify and resolve bugs efficiently.
• Conduct functional coverage analysis and drive coverage closure.
• Mentor junior engineers on verification methodologies and best practices.

Required Qualifications

• Extensive experience with ASIC digital verification, specifically focusing on Interface IP protocols like PCIe, CXL, DDR, and Ethernet.
• Competence in SystemVerilog and UVM methodologies.
• Solid understanding of digital design and verification concepts.
• Experience with simulation tools such as VCS or ModelSim.
• Strong analytical skills and attention to detail.

Education Requirements

A relevant degree in Engineering or a related field is preferred but not specified.