ASIC Digital Verification Engineer - Senior Staff

Role Summary

This position requires a highly skilled ASIC Digital Verification Engineer with extensive experience in verifying complex ASIC designs. The role involves developing verification strategies focused on next-generation High Bandwidth Memory (HBM) products and improving verification methodologies.

Experience Level

Level - Senior

Responsibilities

• Develop and execute comprehensive verification plans for complex ASIC designs.
• Write and maintain advanced testcases using SystemVerilog and UVM methodologies.
• Debug and analyze complex testbench and design-related issues while collaborating with design and mixed-signal teams.
• Automate verification processes using scripting languages like Python or Perl.
• Review design specifications and provide feedback to improve product quality.
• Participate in code reviews, mentor junior engineers, and share best practices.
• Document verification results and methodologies for knowledge sharing.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE or MSEE) with a minimum of 10 years of digital design/verification experience.
• Proven experience with SystemVerilog/UVM for writing and maintaining testcases.
• Strong debugging skills for complex issues in testbench and design.
• Solid understanding of digital circuit design concepts.
• Proficiency in scripting languages for automation.
• Ability to operate independently and collaboratively in a dynamic environment.

Education Requirements

Bachelor’s or Master’s degree in Electrical Engineering (BSEE or MSEE).