ASIC Digital IP Design Verification Architect

Role Summary

The role involves leading the design and verification of ASIC Digital IP processes. The ASIC Digital Verification Architect will implement strategies and methodologies to enhance semiconductor technology at Synopsys.

Experience Level

Senior level position requiring extensive experience in ASIC RTL design and verification.

Responsibilities

The main responsibilities include:

• Defining and developing ASIC RTL design and verification for chips and blocks.
• Creating and executing verification plans focusing on HBM or PCIe/CXL.
• Collaborating with cross-functional teams for design integration.
• Utilizing verification methodologies and tools for high-quality results.
• Mentoring junior engineers and promoting best practices.
• Communicating with stakeholders about project goals.

Requirements

Essential requirements include:

• Extensive experience in ASIC RTL design and verification.
• Deep knowledge of HBM or PCIe protocols and applications.
• Proficiency in advanced verification tools and methodologies.
• Strong problem-solving skills and the ability to work independently.
• Excellent communication skills.

Education Requirements

Information not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.