ASIC Digital Design Verification Staff Engineer
SynopsysJob Title
ASIC Digital Design Verification Staff Engineer
Role Summary
The ASIC Digital Design Verification Staff Engineer will design and implement verification environments to ensure the correctness of Interface IP protocols. The role involves collaboration with design and architecture teams and mentoring junior engineers.
Experience Level
Senior level position with extensive experience in digital design and verification methodologies preferred.
Responsibilities
The key responsibilities include:
- Designing and implementing verification environments for Interface IP protocols.
- Collaborating with design teams to identify and resolve bugs.
- Performing verification tasks including test plans, functional coverage analysis, and coverage closure.
- Mentoring junior verification engineers.
- Conducting design and verification reviews.
- Documenting specifications, test plans, and verification reports.
Requirements
Must-have skills include:
- Proficiency in digital design and verification methodologies.
- Experience with System Verilog and UVM.
- Strong understanding of verification techniques.
- Familiarity with scripting languages such as Python or Perl.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
