ASIC Digital Design Verification, Principal Engineer

Role Summary

This position is for a Principal Engineer specializing in ASIC Digital Design Verification based in Reading, United Kingdom. The engineer will be responsible for overseeing the verification phases of ASIC digital designs, ensuring high-quality performance and compliance with specifications.

Experience Level

Senior level experience is required for this position.

Responsibilities

• Develop verification plans and methodologies for complex ASIC designs.
• Implement systematic verification processes, ensuring compliance with design specifications.
• Collaborate with design teams to identify and resolve verification issues.
• Provide mentorship and guidance to junior engineers within the team.
• Utilize simulation tools and methodologies to enhance verification efficiency.

Requirements

• Extensive experience in ASIC design and verification.
• Strong knowledge of verification methodologies such as UVM, SystemVerilog, or VHDL.
• Ability to work collaboratively in a team environment and communicate effectively.
• Proficient in using industry standard verification tools and software.

Education Requirements

A bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is required. A master's degree is preferred.