The ASIC Digital Design Staff Engineer (Verification) is responsible for working in a collaborative team to develop and validate complex digital mixed-signal designs, focusing on high-speed interface IP. This role requires strong expertise in verification methodologies and tools, contributing to innovative solutions in Data Center, AI/ML, and 5G applications.
Senior level; a minimum of 5 years of experience in design verification is required.
The incumbent will be responsible for:
Candidates should possess the following qualifications:
BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications or related fields.
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
