ASIC Digital Design Staff Engineer

Job Title

ASIC Digital Design Staff Engineer

Role Summary

Senior verification lead responsible for ownership of verification for critical IP blocks. You will define verification strategy, build and maintain subsystem UVM testbenches, drive coverage closure, and mentor verification engineers across Noida and global sites.

Experience Level

Senior — requires substantial hands-on verification experience. The role expects roughly 5+ years of ASIC or FPGA verification experience.

Responsibilities

Lead verification planning and execution for complex IP, ensuring quality and on-schedule delivery.

• Define verification strategy and lead a global team of verification engineers.
• Architect and develop subsystem-level UVM testbenches in SystemVerilog, integrating RTL and behavioral models.
• Write and debug advanced tests, assertions, and protocol checkers for multi-interface designs.
• Define verification plans with measurable coverage goals and drive closure to signoff.
• Manage regression suites, investigate simulation failures, and perform root-cause analysis.
• Collaborate with RTL designers and architects to clarify specifications and ensure correctness.
• Mentor engineers on UVM methodology, debugging, and verification best practices.

Requirements

Technical must-haves for successful candidates and a few desirable skills.

• Must-have: Deep expertise building UVM-based testbenches in SystemVerilog and architecting verification environments.
• Must-have: Proven technical leadership of verification efforts, including test plan definition, coverage closure, and delivering IP to signoff.
• Must-have: Strong experience with at least two protocols from DDR, HBM, PCIe, UCIe, Ethernet, or UALink, including creating protocol checkers and monitors.
• Must-have: Ability to write complex assertions and functional coverage and to debug large integrated testbenches.
• Must-have: Experience owning end-to-end verification deliverables and using coverage metrics to drive decisions.
• Nice-to-have: Hands-on experience with industry-standard coverage analysis tools and metrics extraction workflows.
• Nice-to-have: Prior experience on IP used in AI accelerators, automotive SoCs, or data-center silicon.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or Computer Science. The posting specifies 5+ years of hands-on ASIC or FPGA verification experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.