ASIC Digital Design Staff Engineer

Job Title

ASIC Digital Design Staff Engineer

Role Summary

Own formal property verification and formal sign-off for assigned digital RTL blocks within the IPG Customer Engagement and Infrastructure team. Develop and maintain assertions, formal testbenches, and constraint sets; debug counterexamples and coordinate fixes with designers.

Mentor junior engineers and build reusable formal verification components that accelerate verification and improve design quality.

Experience Level

Senior - 3 to 5 years of hands-on semiconductor verification experience with substantial ownership of formal property verification.

Responsibilities

Primary responsibilities include end-to-end formal verification, tooling, and collaboration with design teams.

• Own formal property verification and drive proofs to closure for assigned RTL blocks through final sign‑off.
• Read specifications and RTL to write SystemVerilog Assertions, assumptions, and cover properties that capture intended behavior and legal input spaces.
• Build and maintain formal testbenches including bind files, helper logic, abstraction wrappers, and constraint sets.
• Run formal tools, tune solver engines and effort settings, and push proof bounds or apply targeted abstractions until proofs converge or root causes are identified.
• Debug counterexamples to determine whether issues are in RTL, properties, or constraints and work with designers to resolve them.
• Review simulation testbenches and specifications to identify missing legal-input assumptions and keep formal constraints aligned with actual usage.
• Track and report property status (proven, covered, falsified, inconclusive) and communicate coverage gaps and open issues to leads.
• Mentor and guide recent graduate and junior engineers on practical formal verification and debugging techniques.

Requirements

Must-have technical skills and experience; preferred items noted.

• 3–5 years of semiconductor verification experience with significant ownership of formal property verification.
• Strong working knowledge of SystemVerilog and SystemVerilog Assertions (concurrent assertions, sequences, properties, assume/assert/cover, bind, clocking blocks).
• Practical experience closing formal proofs: constraint debugging, counterexample trace analysis, reset and clock modeling, and solver tuning.
• Ability to read synthesizable RTL (SystemVerilog or Verilog) and trace waveforms and counterexamples back to design intent.
• Comfortable with Tcl-based formal tool flows (compile/elaborate/check commands) and automated reporting.
• Effective debugging and communication skills to work directly with designers and verification leads.
• Nice-to-have: hands-on experience with commercial formal tools (Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, OneSpin) and prior mentoring experience.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.