ASIC Digital Design Staff Engineer

Job Title

ASIC Digital Design Staff Engineer

Role Summary

Design and deliver RTL for digital and mixed-signal semiconductor IP as part of the FE Design team in Porto. Work across architecture, RTL implementation, synthesis and verification to produce production-quality IP used in automotive, mobile, data center, HPC and AI applications.

The role requires close collaboration with verification, product engineering and global teams to meet timing, power and quality targets and to produce clear design documentation for customers and internal teams.

Experience Level

Senior-level. The posting requests at least 3 years of hands-on ASIC digital design or front-end RTL experience; the title implies a senior/Staff engineer role.

Responsibilities

Key responsibilities include implementation, analysis and cross-team collaboration to deliver RTL that synthesizes, meets timing and integrates into customer designs.

• Design and implement RTL using Verilog/SystemVerilog (and VHDL where applicable) following coding standards and quality checks.
• Participate in architecture exploration and produce design specifications that guide implementation and verification.
• Run synthesis exploration and map constraints; analyze timing and power results and iterate RTL to meet targets.
• Support DFT and ATPG flows and perform coverage analysis.
• Collaborate with verification engineers to define testbenches, debug failures, and close coverage gaps.
• Produce high-quality documentation for customers and internal teams.
• Integrate AI-assisted tools into the design workflow to improve coding, debugging, and code review.

Requirements

The following are the core technical requirements and desirable skills.

• Must-have: At least 3 years of hands-on ASIC digital design / RTL development or front-end design flow experience.
• Must-have: Strong proficiency in RTL HDLs (Verilog, SystemVerilog; VHDL experience where applicable) and behavioral modeling.
• Must-have: Practical experience with synthesis flows, constraints mapping, timing analysis and power optimization in production designs.
• Must-have: Solid understanding of DFT and ATPG methodologies.
• Must-have: Ability to write clear, usable design specifications and technical documentation; strong written and spoken English for global collaboration.
• Must-have: Experience working with verification teams and debugging RTL/timing issues that affect silicon behavior.
• Nice-to-have: Experience with high-speed memory interfaces (DDR, HBM) and mixed-signal IP integration.
• Nice-to-have: Prior use of AI-assisted EDA tools or similar productivity tooling.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related technical field (as stated in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.