ASIC Digital Design Sr Staff Engineer

Job Title

ASIC Digital Design Sr Staff Engineer

Role Summary

Lead architecture and implementation of high-performance RTL for advanced IP cores focused on die-to-die and high-speed communication protocols (consumer and automotive applications). Work within the DesignWare IP Design R&D team at Synopsys' Hyderabad Design Center and collaborate with global sites, verification teams, and customers.

Deliver robust, synthesizable ASIC designs, drive micro-architecture decisions from specs, and mentor designers to maintain high quality and fast time-to-market.

Experience Level

Senior - typically 12+ years of relevant ASIC digital design experience as indicated in the posting.

Responsibilities

Key responsibilities include:

• Architect and implement RTL for high-performance IP cores, with emphasis on die-to-die and high-speed protocols.
• Create architecture and micro‑architecture documents from functional specifications.
• Perform RTL coding (Verilog/SystemVerilog), synthesis, CDC analysis, formal checks, and static timing analysis.
• Debug designs, develop tests, and close design issues through implementation cycles.
• Collaborate with verification to plan and complete verification cycles and achieve coverage targets.
• Interact with customers to clarify requirements and align designs to end-user needs.
• Mentor and technically lead a team of designers across multiple sites.

Requirements

Must-have:

• 12+ years of industry experience in ASIC digital design.
• Proven RTL skills using Verilog/SystemVerilog and experience driving micro-architecture from specs.
• Hands-on experience with synthesis, CDC analysis, formal checking, and static timing analysis.
• Proficiency with high-speed protocols such as Ethernet, DDR, PCIe, CXL, USB, MPHY, UFS, UNIPRO, UCIe or similar.
• Familiarity with P&R-aware synthesis and implementation flows; experience with tools such as Fusion Compiler or equivalent.
• Experience with revision control (e.g., Perforce) and scripting for automation (Perl, Shell, or similar).
• Exposure to IP design quality processes and demonstrated ability to lead and mentor engineering teams.

Nice-to-have:

• Experience in automotive-grade design flows or multi-site/global project execution.
• Additional scripting or automation skills (Python, TCL) and deeper tool-chain ownership.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) or Master of Science in Electrical Engineering (MSEE).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.