ASIC Digital Design Sr Staff Engineer
SynopsysJob Title
ASIC Digital Design Sr Staff Engineer
Role Summary
The role involves leading and executing design-for-testability (DFT) methodologies, including scan insertion and automatic test pattern generation (ATPG) flows for ASIC designs. You will collaborate closely with RTL and verification teams to ensure DFT requirements are integrated early, enhancing product testability and reliability.
Experience Level
Senior-level position requiring extensive hands-on experience with DFT methodologies for complex ASIC designs.
Responsibilities
The key responsibilities include:
- Lead and execute scan insertion and ATPG for ASIC designs.
- Work with RTL and verification teams for early integration of DFT requirements.
- Analyze and resolve DFT-related issues with tools like Spyglass DFT.
- Perform static timing analysis to validate timing closure.
- Collaborate on best practices for DFT methodologies.
- Improve automation scripts and design flows to enhance efficiency.
Requirements
The ideal candidate will possess:
- Extensive hands-on experience with DFT methodologies.
- Proficiency in EDA tools such as Spyglass DFT.
- Strong understanding of digital logic design and RTL coding.
- Demonstrated ability to resolve DFT-related issues.
- Solid scripting skills in TCL, Perl, or Python.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
