ASIC Digital Design Sr Staff Engineer

Job Title

ASIC Digital Design Sr Staff Engineer

Role Summary

Lead verification for critical ASIC/IP subsystems, defining verification strategy and delivering signoff-quality deliverables. You will manage and mentor a team of verification engineers across Noida and global sites while collaborating closely with RTL designers and architects.

Experience Level

Senior — 10+ years of hands-on ASIC or FPGA verification experience.

Responsibilities

Own subsystem verification from planning through signoff and technical leadership of verification engineers.

• Lead verification strategy and execution for critical IP subsystems; coordinate across local and global teams.
• Architect and build subsystem-level UVM testbenches in SystemVerilog, integrating RTL, behavioral models, and protocol checkers.
• Develop advanced test scenarios, assertions, and checkers for complex multi-interface designs.
• Define verification test plans with measurable coverage goals; track functional and code coverage and drive closure to signoff.
• Manage regression suites, debug simulation failures, perform root cause analysis, and ensure timely resolution.
• Collaborate with RTL designers and architects to clarify specifications and ensure functional correctness.
• Mentor engineers on UVM methodology, debugging techniques, and verification best practices.

Requirements

Key technical qualifications and hands-on skills required to perform the role.

• 10+ years of hands-on ASIC or FPGA verification experience, including technical leadership of verification efforts.
• Deep expertise building UVM-based testbenches in SystemVerilog; experience architecting new verification environments.
• Proven track record defining test plans, driving coverage closure, and delivering IP to signoff.
• Strong experience with at least two of: DDR, HBM, PCIe, UCIe, Ethernet, UALink; including writing protocol checkers and interface monitors.
• Ability to write complex assertions, functional coverage models, and debug difficult simulation failures across large testbenches.
• Experience owning end-to-end verification deliverables: planning, regression management, metrics closure, and final signoff.
• Hands-on proficiency extracting and acting on verification metrics using industry-standard coverage tools and methodologies.
• Effective communicator who provides actionable technical feedback and can operate in hands-on and leadership modes simultaneously.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or Computer Science.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.