ASIC Digital Design Sr. Staff Engineer

Role Summary

The ASIC Digital Design Sr. Staff Engineer will lead the functional verification of advanced IP designs, particularly in the domain of high-speed serial link PHYs such as USBx, PCIe, and SATA. The role includes collaboration with architecture and design teams to set and meet verification goals while ensuring compliance with industry standards.

Experience Level

10-15 years of experience in ASIC digital design and verification.

Responsibilities

• Lead the functional verification process for advanced IP designs.
• Collaborate with architecture and design teams to define verification goals.
• Develop and oversee test methodologies ensuring compliance with UVM and SystemVerilog.
• Build and maintain verification environments using constraints and coverage metrics.
• Execute and debug regression simulations and analyze results.
• Create detailed test plans and monitor progress.
• Implement Agile practices within the team.
• Mentor junior engineers and promote a collaborative environment.
• Report technical status, risks, and solutions to management.

Requirements

• Hands-on experience in ASIC digital design and verification, focusing on IP-level functional verification.
• Expertise in verification methodologies like UVM and SystemVerilog.
• Strong background in high-speed serial protocols (SERDES, USB, PCIe, SATA).
• Experience in developing verification environments and achieving coverage goals.
• Demonstrated regression management and quality assurance experience.
• Proficiency in Agile practices within engineering teams.

Education Requirements

Bachelor's degree in Electrical Engineering or related field is typically required.