ASIC Digital Design Senior Staff Engineer - Verification

Role Overview

The position is for a Senior Staff ASIC Engineer specializing in digital design verification. This role is part of an engineering team responsible for the development and validation of complex digital mixed-signal IP solutions.

Role Summary

You will utilize your extensive expertise in ASIC Digital Design and verification processes to ensure the delivery of high-performance silicon chips. This position requires collaborative work in a dynamic environment at Synopsys, a company leading in chip design and verification technology.

Experience Level

Applicants should have a minimum of 8 years of experience in design verification, demonstrating proficiency with simulation tools and methodologies relevant to digital and mixed-signal designs.

Responsibilities

• Design and validate complex digital mixed-signal IP solutions.
• Plan and execute test strategies, coverage metrics, and assertions.
• Create functional verification environments based on specifications.
• Implement advanced verification techniques including functional coverage and formal verification.
• Debug simulations effectively and perform RTL, GLS, and co-simulations.
• Contribute to technical reviews and continuous process improvement.
• Assist customers with integrating IP into their systems.

Requirements

A solid background in Electronics Engineering, preferably with a BS/MS/PhD in a relevant field. Candidates must have experience with VCS/Verdi and formal verification tools, as well as familiarity with UPF and UVM methodologies.

Education Requirements

Bachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, or Telecommunications.