ASIC Digital Design Senior Staff Engineer

Job Title

ASIC Digital Design Senior Staff Engineer

Role Summary

As a Senior Staff Engineer in ASIC Digital Design at Synopsys, you will leverage your expertise to develop high-performance silicon chips. You will be responsible for ensuring reliable and efficient verification processes within a collaborative environment.

Experience Level

5+ years of relevant experience in ASIC Digital Verification.

Responsibilities

• Developing detailed testplans and functional coverage models to ensure robust verification of training firmware on RTL PHY models.
• Implementing scalable testbench infrastructure and creating comprehensive test cases for various scenarios.
• Collaborating with team members through technical reviews to enhance product quality.
• Debugging complex verification challenges and researching emerging technologies to improve processes.
• Mentoring junior engineers to foster skill development and leadership capabilities.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• Expertise in Verilog, SystemVerilog, and IC design flow, including simulation tools.
• Proficiency in scripting languages (Python, Perl, Bash).
• Strong understanding of digital logic principles and verification methodologies, including UVM.
• Experience with DDR interface protocols and familiarity with assertion verification techniques.
• Hands-on experience with Linux environments and regression systems.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.