ASIC Digital Design Senior Staff Engineer

Role Summary

We are looking for an ASIC Digital Design engineer with extensive knowledge of high-speed digital and mixed-signal interfaces. The ideal candidate will work collaboratively in a technically challenging environment, focusing on RTL design and physical implementation in a team specializing in High Bandwidth Memory (HBM) PHY IP.

Experience Level

This role requires 7-10 years of hands-on experience in ASIC design.

Responsibilities

• Develop RTL designs for High Bandwidth Memory (HBM) PHY IP.
• Translate architectural requirements into high-performance RTL implementations using SystemVerilog and Verilog.
• Collaborate with teams across analog, mixed-signal, and physical design.
• Address physical implementation requirements and solve challenges around timing closure and power efficiency.
• Create detailed specification documents and provide technical guidance.
• Automate design and verification tasks through scripting.
• Support the complete ASIC and IP development lifecycle from concept to production.

Requirements

• 7-10 years of experience in RTL design for high-speed digital and mixed-signal interfaces.
• Proficiency in SystemVerilog and Verilog for RTL development.
• Strong background in design techniques including timing closure and low power strategies.
• Experience with ASIC and IP development, DFT/DFM, and complex hardware debugging.
• Ability to write clear specification documents.
• Preferred experience with DDR/HBM DRAM and UCIe technologies.

Education Requirements

A degree in Electrical Engineering or a related field is typically required for this position.