ASIC Digital Design Principal Engineer
SynopsysRole Summary
The ASIC Digital Design Principal Engineer is a hands-on technical leader responsible for mixed-signal verification and ASIC development. The role involves implementing complex test plans for HPC DSP-based SERDES PHY products and collaborating with various stakeholders to ensure project success.
Experience Level
Senior level with 10+ years of ASIC development and mixed-signal verification experience required.
Responsibilities
Key responsibilities include:
- Implementing Unified Test Plans for HPC DSP-based SERDES PHY products.
- Building and maintaining robust verification environments using UVM methodology and SystemVerilog.
- Developing automation scripts using Shell, Perl, Python, C++, and AI-based approaches.
- Collaborating with product stakeholders to resolve technical challenges.
- Creating comprehensive test plans for high-speed data recovery circuits.
- Sharing best practices and knowledge to drive improvement within the team.
Requirements
Must-have requirements:
- 10+ years of experience in ASIC development and mixed-signal verification.
- Expertise in PCIe, Ethernet protocols, and digital signal processing.
- Advanced skills in SystemVerilog and UVM methodology.
- Proficiency in scripting languages: Shell, Perl, Python, C++.
- Strong organization and communication skills.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
