ASIC Digital Design Principal Engineer

Role Summary

As a Principal ASIC Digital Design Engineer at Synopsys, you will be involved in designing and verifying advanced digital circuits for PAM-based SerDes PHY IP. You will be a key contributor in delivering robust solutions and will work in dynamic environments, pushing the boundaries of semiconductor technology.

Experience Level

Minimum 10 years of industry experience in digital design and verification is required.

Responsibilities

• Designing and verifying advanced digital circuits for PAM-based SerDes PHY IP.
• Developing RTL code and crafting complex system-level testbenches in Verilog.
• Defining synthesis constraints and resolving timing issues.
• Addressing Clock/Reset domain crossing challenges using CDC/RDC tools.
• Enhancing and maintaining existing SERDES PHY IPs to support evolving customer requirements.
• Collaborating with Application Engineers and other teams to ensure successful product deployment.
• Mentoring junior engineers and fostering knowledge sharing.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE or MSEE).
• Familiarity with Verilog and VCS; knowledge of synthesis tools is required.
• Understanding of digital design methodologies, ATE production testing, and DFT.
• Scripting experience in Shell, Perl, Python, and TCL is a plus.
• Good theoretical and practical understanding of digital signal processing is a strong plus.

Education Requirements

Bachelor’s or Master’s degree in Electrical Engineering (BSEE or MSEE).