ASIC Digital Design, Principal Engineer
SynopsysJob Title
ASIC Digital Design, Principal Engineer
Role Summary
Lead the design and delivery of digital ASIC blocks and subsystems for complex SoC projects. This onsite role is part of the ASIC Digital Design team in Dublin and requires close collaboration with verification, physical implementation, system architects, and program management to produce production-quality RTL and implementation-ready deliverables.
Work focuses on RTL architecture, synthesis-ready design, timing closure, and mentoring other engineers to meet performance, power, and area targets.
Experience Level
Senior / Principal. Typical guideline: Principal engineer level (commonly 10+ years of ASIC digital design or equivalent practical experience).
Responsibilities
The role owns technical leadership for digital design workstreams and ensures deliverables meet project targets.
- Define and implement RTL architecture and coding standards for complex digital blocks.
- Develop synthesis-ready RTL, constraints, and clocking/reset strategies.
- Drive timing closure activities and coordinate with synthesis/place-and-route/physical design teams.
- Collaborate with verification teams to ensure testability and functional correctness.
- Mentor and review work of junior and mid-level engineers; lead design reviews and deliverable handoffs.
- Identify and mitigate technical risks; optimize for power, area, and performance trade-offs.
- Contribute to toolflow and methodology improvements for digital design and signoff.
Requirements
Core technical requirements and desirable skills.
- Must-have: Extensive ASIC digital design experience with RTL development (SystemVerilog/Verilog), synthesis, timing analysis, and clocking/reset design.
- Must-have: Proven track record leading design projects to tape-out or equivalent production delivery.
- Must-have: Experience with industry EDA flows (synthesis, STA, equivalence checking, simulation) and common scripting (Tcl, Perl, Python) for automation.
- Must-have: Strong debugging and problem-solving skills across RTL, synthesis, and timing domains.
- Nice-to-have: Experience with low-power design techniques, multi-voltage domains, and advanced process nodes.
- Nice-to-have: Familiarity with formal verification, UPF power intent, or hardware-software co-design.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
