ASIC Digital Design Principal Engineer

Role Summary

The ASIC Digital Design Principal Engineer role involves developing innovative verification strategies for complex mixed-signal IP, focusing on high-performance silicon chips for networking and connectivity applications.

Experience Level

10+ years of ASIC verification experience required, with a strong foundation in digital and mixed-signal domains.

Responsibilities

• Develop comprehensive test plans for complex mixed-signal IP, detailing verification strategies and coverage goals.
• Design and implement UVM-based testbenches using constraint-random verification methodologies to ensure thorough validation.
• Enhance and modify testbench components to support evolving product features.
• Write advanced SystemVerilog tests to validate digital and mixed-signal interaction.
• Run RTL and GLS regressions, analyze failures, and drive issue resolution working closely with design and architecture teams.
• Achieve code and functional coverage goals ensuring verification completeness.
• Explore opportunities for AI adoption to optimize verification flows.

Requirements

The ideal candidate will possess:

• Hands-on experience writing complex SystemVerilog test cases for advanced verification scenarios.
• Proven expertise in developing UVM-based test benches and utilizing constraint-random methodologies.
• Proficiency in scripting with languages such as Python for task automation.
• Strong analytical thinking and problem-solving abilities.
• Excellent organizational and communication skills.
• The ability to collaborate across multiple design teams and disciplines.

Education Requirements

No specific education requirements mentioned; however, relevant experience and expertise are critical components for consideration.