ASIC Digital Design Engineer - Staff

Role Summary

You are a highly experienced engineering professional passionate about verification and digital design methodologies, possessing at least 5 to 10 years of strong experience in IP and SoC verification.

Experience Level

Level - Senior

Responsibilities

• Implement reference and unified verification flows for Synopsys digital IP products using leading EDA tools.
• Build robust, scalable verification infrastructures from the ground up to support diverse projects.
• Partner with global teams to define and propagate best-in-class verification methodologies.
• Lead and mentor junior engineers, fostering a culture of technical growth within the team.
• Drive technical initiatives and manage high-impact assignments for timely deliverables.
• Collaborate with tool development teams to influence product evolution and optimize workflows.
• Troubleshoot and refine verification processes in support of internal stakeholders.

Requirements

• Minimum 5 to 10 years of hands-on experience in IP/SoC verification.
• Strong expertise in Synopsys verification tools (VCS, Verdi, etc.).
• Experience in architecting and implementing verification flows for complex digital designs.
• Solid programming and scripting skills (SystemVerilog, UVM, Tcl, Python, etc.).
• Bachelor’s degree in electronics, electrical, or computer engineering (advanced degrees a plus).
• Proficient in multi-tasking and managing technical projects independently.
• Excellent documentation and communication skills across global teams.

Education Requirements

Bachelor’s degree in electronics, electrical, or computer engineering; advanced degrees are a plus.