ASIC Digital Design Engineer
SynopsysJob Title
ASIC Digital Design Engineer
Role Summary
Design and implement high-frequency digital ASIC IP and full-chip flows focused on in-chip sensors and silicon reliability monitors. Work on RTL-to-GDS implementation, digital backend, STA, physical verification, and signoff to deliver production silicon.
Join a cross-functional engineering team collaborating with architects, circuit designers, and verification engineers to develop and productize SLM (silicon lifecycle monitoring) monitors and related reliability solutions.
Experience Level
Mid-level — typically requires 5+ years of relevant industry experience.
Responsibilities
Key responsibilities include design, implementation, and signoff of digital ASIC IP and chip-level monitors, and developing related flows and methodologies.
- Conceptualize, design, and productize RTL-to-GDS implementation for SLM monitors using standard ASIC flows.
- Design on-chip monitors for process, voltage, temperature, glitch, and droop to support silicon biometrics and reliability.
- Perform digital backend tasks: synthesis, pre-layout STA, SDC constraints development, floorplanning, bump placement, power planning, placement, CTS, and routing.
- Implement multi-voltage design techniques (UPF/VCLP) and ensure proper power planning for signoff.
- Drive post-layout STA, develop timing and functional ECOs, and support timing signoff for high-frequency IP closure.
- Execute physical verification and signoff activities: DRC, LVS, PERC, ERC, antenna checks, EMIR, and power signoff.
- Collaborate with architects and circuit designers to create and refine flows, methodologies, and closure strategies across design corners.
Requirements
Must-have technical skills and experience. Degrees are listed separately under Education Requirements.
- Hands-on experience in Physical Design, Physical Verification, pre- and post-layout STA, and EMIR/power signoff.
- Practical experience with DRC, LVS, DFM cleaning, and timing closure processes.
- Proficiency with digital design and EDA tools (experience with Synopsys tool suite such as Fusion Compiler, VCLP, PrimeTime, IC Validator, RedHawk preferred).
- Experience with advanced process nodes (14nm down to 2/3nm) and successful tape-outs.
- Understanding of OCV/POCV, derates, crosstalk, and design margins for timing and reliability.
- Scripting skills for flow automation and methodology development (TCL, Perl or similar).
- Experience generating ECOs for timing closure and device-reliability-driven fixes.
Education Requirements
Bachelor's (BS/B.Tech) or Master’s (MS/M.Tech) degree in Electrical Engineering is required. The posting specifies 5+ years of relevant industry experience. (Degrees and field-of-study are extracted from the original posting.)
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
