ASIC DFT Technical Leader

Job Title

ASIC DFT Technical Leader

Role Summary

Senior technical leader in the Silicon One development organization responsible for driving Design-for-Test (DFT) strategy and execution across front-end RTL, backend physical design, and post-silicon validation. You will define DFT requirements early, own DFT quality through implementation and silicon bring-up, and support physical-design signoff activities.

Experience Level

Senior — requires at least 10 years of relevant experience.

Responsibilities

Lead DFT activities across the full chip development lifecycle and collaborate with RTL, backend, and validation teams.

• Define and drive DFT requirements and architecture early in the design cycle.
• Collaborate with frontend (RTL) and backend physical design teams to ensure testability and signoff readiness.
• Lead ATPG flow and integration of test IP (scan, BIST, memory BIST, boundary scan).
• Manage gate-level simulation, timing-aware test verification, and debug activities.
• Drive post-silicon validation and debug using ATE patterns and P1687-based infrastructures.
• Contribute to DFT CAD/toolflow development and test methodology improvements.
• Support integration of DFT IP and custom DFT logic into production chips.

Requirements

Key technical skills and experience required and preferred for the role.

Must-have:

• 10+ years working in DFT, test, or silicon engineering.
• Experience with JTAG protocols, scan architectures, BIST (including memory BIST) and boundary scan.
• Practical experience with ATPG and EDA toolsets (examples: TestMax, Tetramax, Tessent, PrimeTime).
• Gate-level simulation and debugging experience, including use of VCS or similar simulators.
• Post-silicon validation and debug experience; familiarity with ATE patterns and P1687.

Nice-to-have:

• Verilog/SystemVerilog design experience for custom DFT logic and IP integration.
• DFT CAD development experience: test architecture, methodology, and infrastructure.
• Test static timing analysis (Test STA) and test-timing validation skills.
• Experience with SystemVerilog-based logic equivalency checking and test-timing validation.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required. The posting specifies at least 10 years of experience; no certifications were listed. (Degree requirement extracted from the minimum qualifications.)

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).