ASIC DFT Technical Leader

Job Title

ASIC DFT Technical Leader

Role Summary

Join the Common Hardware Group (CHG) within the Silicon One development organization as an ASIC Technical Leader focused on Design-for-Test (DFT). The role partners with front-end RTL and back-end physical design teams to define and drive DFT requirements early in the design cycle and through implementation and post-silicon validation.

This position leads DFT strategy, test architecture, and defect-detection quality processes for next-generation networking ASICs.

Experience Level

Senior — requires at least 10 years of relevant experience.

Responsibilities

Key responsibilities include defining DFT strategy, coordinating across design teams, and leading test and validation activities through post-silicon phases.

• Collaborate with RTL and physical design teams to specify DFT requirements and ensure early integration.
• Define and implement scan, BIST, memory BIST and boundary-scan architectures.
• Lead ATPG flows and EDA tool usage for test insertion and coverage closure.
• Oversee gate-level simulation, test-timing validation, and debug activities.
• Drive post-silicon validation and debug, including ATE pattern usage and P1687 access where applicable.
• Contribute to physical design signoff activities related to test and timing.
• Mentor engineers and drive DFT/process improvements across projects.

Requirements

Must-have technical skills and experience; preferred items noted separately.

• Extensive experience in DFT, test engineering, and silicon engineering.
• Experience with JTAG, scan architectures, BIST (including memory BIST) and boundary scan.
• Hands-on experience with ATPG and EDA tool flows (examples: TestMax, Tetramax, Tessent tool sets, PrimeTime).
• Experience with gate-level simulation and debugging using VCS or equivalent simulators.
• Post-silicon validation and debug experience; familiarity with ATE patterns and P1687.
• Strong communication and cross-functional collaboration skills to align RTL, physical design, and validation efforts.

Nice-to-have / Preferred:

• Verilog experience for developing DFT logic and integrating DFT IP; familiarity with functional verification.
• DFT CAD development experience: test architecture, methodology and infrastructure.
• Test static timing analysis and test-timing validation skills.
• Verification skills such as SystemVerilog logic equivalency checking.

Education Requirements

Required: Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.

Compensation note: For U.S. and Canada locations the posted starting salary range is $186,900 to $267,700 (base pay). Higher ranges for specific locations are listed in the employer’s posting.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).