ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Join Cisco's Common Hardware Group (CHG) within the Silicon One development organization as an ASIC engineer focused on Design-for-Test (DFT). The role drives DFT requirements early in the design cycle and follows those features through implementation and post-silicon validation.

This position works with front-end RTL, backend physical design, verification, and multi-functional teams to develop DFT IP, integrate test logic, and improve testability and diagnostics for networking ASICs.

Experience Level

Mid-level — at least 5 years of relevant industry experience (minimum 5 years required as stated in the posting).

Responsibilities

Primary responsibilities span DFT IP development, integration, and post-silicon validation.

• Implement hardware DFT features supporting ATE, in-system test, debug and diagnostics.
• Develop innovative DFT IP and integrate testability features at full-chip RTL level.
• Collaborate with RTL, physical design, and verification teams to enable test-logic integration and validation across implementation and post-silicon phases.
• Drive DFT and quality processes through implementation flow and post-silicon validation; lead debug with minimal mentorship.
• Contribute to DFT and physical design strategies for new device models (bare die, stacked die) and reusable test/debug approaches.
• Work with ATE patterns and standards such as P1687 and support ATPG flows.

Requirements

Must-have technical skills and experience for successful performance in this role.

• 5+ years of experience in DFT, test, and silicon engineering (experience level noted; degree details are under Education Requirements).
• Experience with JTAG protocols, scan architectures, BIST (including memory BIST) and boundary scan.
• Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime.
• Experience with gate-level simulation and debugging using VCS or equivalent simulators.
• Post-silicon validation and debug experience; familiarity with ATE patterns and P1687 is expected.
• Strong problem-solving and ability to craft solutions and debug with minimal mentorship.

Nice-to-have:

• Verilog design experience for custom DFT logic and IP integration.
• Test static timing analysis and SystemVerilog verification skills (logic equivalency, test-timing validation).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).