ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Join Cisco's Silicon One team focused on high-performance networking ASICs. This role owns Design-for-Test (DFT) requirements and execution across RTL, physical implementation, and post-silicon validation phases.

The engineer will collaborate with front-end RTL and backend physical design teams to define and drive DFT strategy, tooling, and debug to production-quality silicon.

Experience Level

Mid-level - requires at least 3 years of relevant ASIC DFT, test, or silicon engineering experience.

Responsibilities

Primary responsibilities include defining and driving DFT across the chip lifecycle and supporting post-silicon validation and debug.

• Define DFT requirements early with RTL and physical design teams and ensure correct implementation through signoff.
• Specify and integrate scan, BIST (including memory BIST), boundary-scan and JTAG architectures.
• Run ATPG flows and manage DFT toolchains (e.g., TestMax, Tetramax, Tessent, PrimeTime).
• Perform gate-level simulation, debug with VCS or similar simulators, and validate test timing.
• Lead post-silicon validation, debug ATE patterns, and work with P1687 methodologies where applicable.
• Collaborate across verification, physical design, and manufacturing teams to resolve testability and quality issues.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Minimum 3 years of ASIC DFT, test, or silicon engineering experience.
• Practical experience with JTAG, scan chains, and BIST architectures (memory BIST, boundary scan).
• Hands-on experience with ATPG and EDA tool flows (TestMax, Tetramax, Tessent tool sets, PrimeTime).
• Gate-level simulation and debug experience using VCS or equivalent simulators.
• Post-silicon validation and debug, including working with ATE patterns and P1687.
• Ability to coordinate DFT efforts across RTL, physical design, and validation teams through implementation and post-silicon phases.

Nice-to-have:

• Verilog design experience for custom DFT logic and IP integration.
• Static timing analysis and test-timing validation experience.
• SystemVerilog logic equivalency checking and advanced verification skills.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).