ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Join the Memory PHY development team to lead DFT implementation and test methodology development across the ASIC lifecycle. The role focuses on ensuring manufacturability, fault coverage, and production yield through DFT architecture, pattern generation, and silicon bring-up support.

Experience Level

Mid-level - requires 3+ years of DFT experience.

Responsibilities

Primary responsibilities include:

• Architect, implement, and validate DFT methodologies and flows.
• Define and implement DFT features such as scan, compression, MBIST, LBIST, and boundary scan (JTAG).
• Develop ATPG flows; perform pattern generation and fault coverage analysis.
• Perform DFT synthesis, scan insertion, and test timing closure.
• Collaborate with Design, Verification, Physical Design, and Product Engineering teams throughout the ASIC development lifecycle.
• Support silicon bring-up and production yield improvement activities.

Requirements

Must-have and preferred qualifications:

• Minimum 3 years of hands-on ASIC DFT experience with DFT flows and tools.
• Practical experience with scan insertion, ATPG, MBIST/LBIST, and compression.
• Strong communication skills in Mandarin and English.
• Nice-to-have: familiarity with HBM, DDR, and UCIe protocols.

Education Requirements

BS or MS degree in Electrical Engineering or Computer Engineering.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.