ASIC Design Verification Engineer

Role Overview

The ASIC Design Verification Engineer role involves joining a team dedicated to developing silicon products for Ethernet systems within the Cloud, particularly focusing on AI/ML workflows. Engineers in this position will contribute to the development of high-performance Ethernet solutions with an emphasis on power efficiency.

Experience Level

We seek candidates with a strong background in verification methodologies and a minimum of 3-8 years of experience depending on their educational qualifications. A Bachelor's degree coupled with 8+ years of experience, a Master's degree with 6+ years, or a PhD accompanied by 3+ years of experience is required.

Responsibilities

The engineer will be responsible for verifying new designs, ensuring coverage closure through Constrained Random Verification methodologies, and collaborating with global design and architecture teams. Candidates may also have opportunities for technical leadership while working in a dynamic market.

Requirements

Strong teamwork skills and self-motivation are critical. Proficiency with System Verilog (including TB structures such as Classes, SVA) and UVM is preferred, alongside scripting skills in Python or Perl. Applicants should have a proven record in driving project completion and may include a range of tools and languages to achieve success in their role.

Education Requirements

A Bachelor's degree in a relevant engineering field is mandatory, with additional qualifications considered at higher educational levels (Master's or PhD). A total experience of at least 3-8 years in related roles is expected based on the candidate's educational background.