ASIC Design Engineer II

Job Title

ASIC Design Engineer II

Role Summary

Work on the Cloud-Scale Machine Learning Acceleration team (Annapurna Labs / AWS) to design and implement ASIC hardware for data-center ML inference. The role focuses on RTL microarchitecture and implementation to deliver high-performance, power- and area-efficient designs.

Experience Level

Mid-level. The role expects approximately 3+ years of design or architecture experience in ASIC or system design.

Responsibilities

Deliver RTL and microarchitectures that meet performance, power, and area targets and collaborate across teams to integrate and validate designs.

• Develop and implement high-performance, area- and power-efficient SystemVerilog RTL and microarchitectures.
• Produce synthesis- and timing-clean RTL with appropriate constraints.
• Analyze architectures and perform trade-off studies between features, performance, power, and area.
• Execute linting and clock-domain-crossing (CDC) checks to ensure design quality.
• Collaborate with architects, designers, verification engineers, and validation teams throughout the design cycle.

Requirements

Must-have technical skills and practical experience.

• Proficiency in SystemVerilog and RTL implementation.
• Experience delivering synthesis- and timing-clean designs and writing appropriate constraints.
• Experience with lint and CDC quality flows.
• Familiarity with interconnects, DMA engines, memory sub-systems, and system-level architecture.
• Strong analytical and problem-solving skills and experience collaborating with cross-functional engineering teams.

Education Requirements

Bachelor's degree or equivalent practical experience in a relevant field (the posting states "Bachelor's degree or equivalent").

About the Company

Company: Annapurna Labs

Headquarters: Cupertino, CA, USA

Annapurna Labs is a semiconductor design company within Amazon Web Services that develops custom SoCs, ASICs and networking processors for cloud data centers and storage infrastructure.