ASIC Design and STA Engineer
Join NVIDIA's Networking Silicon engineering team to lead static timing analysis (STA) and timing convergence for high-speed communication ASICs and chiplets. Work across floorplanning, clock planning, timing integration, and signoff flows to deliver high-throughput, low-latency devices for AI platforms.
Position may be based in Bengaluru or Hyderabad, India, and involves close collaboration with CAD, logic design, DFT, PD, and RTL teams.
Mid-level (no explicit years of experience provided).
Primary engineering responsibilities and collaboration areas.
Key skills and attributes required or preferred for the role.
B.Sc./M.Sc. in Electrical Engineering or Computer Engineering; or B.Tech/M.Tech in Computer Science, Electronics & Communication, or a related technical field. The posting emphasizes a strong academic background and/or pursuing these degrees.
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
