Applications Engineering, Engineer

Job Title

Applications Engineering, Engineer

Role Summary

As an Applications Engineer on the Customer Success Group Applications Engineering team in Bangalore, you will support customers adopting Synopsys RTL-to-GDSII physical design tools. The role focuses on driving evaluations, debugging placement/timing/routing issues, and developing methodology for advanced-node designs.

Work closely with account managers and product teams to translate customer problems into technical solutions and to improve tool adoption and methodologies.

Experience Level

Mid-level — typical guidance: Bachelor's +4 years or Master's +2 years in ASIC/physical design; equivalent practical experience considered.

Responsibilities

You will run customer evaluations, provide demos and trainings, debug physical design issues, and contribute methodology and benchmarking.

• Support customer evaluations and benchmarks of physical design flows from placement through routing and timing closure.
• Deliver technical demonstrations and training focused on advanced-node challenges (sub-7nm/sub-5nm).
• Debug placement, clock tree synthesis, routing, and timing optimization issues with customer design teams.
• Collaborate with account managers on technical account planning and tool adoption strategies.
• Manage multiple customer engagements and prioritize work across evaluations and sales cycles.
• Develop and refine design methodologies and AI-assisted optimization techniques for advanced nodes.
• Perform competitive benchmarking and provide data-driven comparisons against alternative tools.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• Hands-on experience with place-and-route tools and physical design implementation (placement, optimization, CTS, routing).
• Working knowledge of Synopsys backend tools such as Fusion Compiler or ICC2, or equivalent P&R platforms.
• Understanding of RTL-to-GDSII flows and interactions between synthesis, implementation, and timing signoff.
• Experience addressing advanced-node design challenges (timing closure, routing congestion) at sub-7nm/sub-5nm.
• Ability to run evaluations, produce benchmarks, and present technical findings to customers and internal teams.
• Strong communication and customer-facing skills; ability to manage multiple concurrent evaluations.
• Nice to have: experience with static timing analysis tools (PrimeTime) and logic synthesis tools (Design Compiler or Fusion Compiler).

Education Requirements

Bachelor's degree in Electrical Engineering (or equivalent) with 4+ years of ASIC design experience, or Master's degree with 2+ years of experience. Equivalent practical experience is accepted.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.