Analog Models and Verification Engineer/Architect

Role Overview

We are seeking a skilled Analog Models and Verification Engineer/Architect with experience in mixed-signal systems to enhance our chip design and verification process. The role involves creating high-fidelity behavioral models for advanced analog circuits to improve the verification workflow related to high-speed SerDes technology.

Position Summary

The engineer will closely collaborate with various engineering teams to simulate and sign off on models, ensuring they meet high standards of accuracy and performance. This role is crucial for maintaining quality assurance across our connectivity products and involves working from our Chandler, AZ location.

Experience Level

The position requires a candidate with a minimum of 7 years of relevant experience in the industry, particularly in verification engineering and mixed-signal systems.

Primary Responsibilities

• Extract necessary details from analog circuit teams and rigorously verify high-fidelity models against SPICE simulations and silicon data.
• Develop and refine behavioral models for high-speed SerDes blocks including TX/RX, ADC, DAC, and PLL.
• Ensure accuracy in model functionalities and performance metrics.
• Work with digital design teams to ensure comprehensive model verification.
• Drive model optimization for better simulation speed and accuracy.
• Establish best practices in model creation and verification.
• Mentor and support junior team members in methodologies and innovations.

Skills and Qualifications

Applicants should possess advanced knowledge of Verilog, SystemVerilog, and experience with analog and mixed-signal verification flows. Strong programming skills in scripting languages such as Python and C/C++ are required. Familiarity with verification environments and performance measurement in analog circuits is essential.

Education Requirements

A Bachelor's, Master's, or Ph.D. in Electrical or Computer Engineering is required for this position.