Analog/Mixed Signal Verilog Modeling Design Engineer
BroadcomRole Summary
The Analog/Mixed Signal Verilog Modeling Design Engineer will develop Digital-Mixed Signal (DMS) models for various analog IPs and support analog/mixed signal models for chip verification in conjunction with the design team.
Experience Level
Senior level; requires a Bachelor's degree and 8+ years of related experience.
Responsibilities
The engineer will be responsible for the following tasks:
- Developing DMS models of analog IPs using SystemVerilog.
- Interfacing with the analog design and chip DV teams.
- Understanding Verilog-AMS and implementing good RTL coding practices.
- Running SV vs. schematic verification for leaf SV models.
- Utilizing Cadence tools for simulation and scripting languages like TCL, Perl, or Python.
- Employing AI tools for generating analog SV models and testbenches.
Requirements
The following skills and experiences are required:
- Proficiency in SystemVerilog and Verilog-AMS.
- Good knowledge of analog circuits (e.g., LDOs, SAR ADCs).
- Experience with Cadence simulation tools (ncsim, xrun, vcs).
- Hands-on scripting skills in TCL, Perl, or Python.
- Experience with AI tools for model generation.
Education Requirements
Bachelor's degree required.
About the Company
Company: Broadcom
Headquarters: Irvine, California, United States
Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.
