The Analog Layout Staff Engineer will lead the design and development of DDR/HBM PHY layout IPs for next-generation technologies at Synopsys. This role involves collaborating with a team of engineers to integrate advanced silicon IP into customer SoCs while ensuring high-quality standards are met.
Senior level with a minimum of 5 years of relevant experience in layout design.
The key responsibilities include:
Must-have qualifications:
BTech/MTech degree in Electrical Engineering, Electronics, or related field is required.
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
