Analog Layout Design Sr. Engineer

Role Summary

This position requires an experienced Analog Layout Senior Engineer with a strong emphasis on custom layout design.

Experience Level

5+ years of experience in custom layout design is necessary.

Responsibilities

• Work on custom layout Analog IPs including High Speed IOs, PLL, DLL, Bandgap, and High Speed macros for PHY.
• Floor planning, power design, signal routing strategy, EMIR awareness, and parasitic optimization.
• Ensure design meets performance with minimum area and optimal yield through Analog Layout techniques.
• Enhance layout flow for improved design processes.
• Conduct layout verification for DRC/LVS/ERC/ANT/ESD/DFM.
• Participate in design reviews and collaborate with Place and Route engineers and the Package team.
• Lead a layout team and mentor junior layout engineers or interns.

Requirements

• BS in Electronics Engineering, Electromechanics, Telecommunications or equivalent.
• Experience with Cadence and Synopsys layout entry tools and Mentor Calibre, Synopsys ICV for layout verification.
• Strong understanding of semiconductor fabrication processes and MOSFET fundamentals.
• Experience in ESD, Latchup, Antenna, EMIR layout techniques.
• Effective English communication skills.

Education Requirements

BS in Electronics Engineering, Electromechanics, Telecommunications.