Analog Layout Design Senior Engineer

Role Summary

The Analog Layout Design Senior Engineer will work on custom layout for various Analog IPs and enhance layout design processes. The role involves collaboration with global teams for design integration and mentoring junior engineers.

Experience Level

Senior level with at least 5 years of experience in custom layout.

Responsibilities

The primary responsibilities include:

• Designing custom layout Analog IPs including High-Speed IOs, PLLs, DLLs, and Bandgap.
• Performing floor planning, power design, and signal routing.
• Applying layout techniques for performance and yield optimization.
• Building and improving layout design processes.
• Conducting layout verification processes including DRC/LVS/ERC checks.
• Mentoring junior layout engineers and leading layout teams.
• Collaborating across teams in different locations to ensure project success.

Requirements

Key requirements include:

• BS in Electronics Engineering or related fields.
• 2+ years of experience in custom layout design.
• Proficiency with Cadence and Synopsys layout tools.
• Experience with Mentor Calibre and Synopsys ICV for layout verification.
• Strong understanding of semiconductor processes, MOSFET fundamentals, and high-speed layout techniques.
• Good communication skills in English.

Education Requirements

BS in Electronics Engineering, Electromechanics, or Telecommunications.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.