Analog Layout Design Engineer

Job Title

Analog Layout Design Engineer

Role Summary

Design and optimize complex analog and mixed-signal IC layouts to meet performance, area, and reliability targets. Work within analog design teams and with process, verification, and packaging groups to deliver robust floorplans, power grids, ESD and bump layouts, and parasitic-aware designs.

Experience Level

Mid-level — typically 3+ years of relevant industry experience with a Bachelor’s degree, or 2+ years with a Master’s degree.

Responsibilities

Primary responsibilities include detailed layout creation, verification, and methodology improvements:

• Design complex analog signal circuit layouts from specifications.
• Perform layout verification and reliability checks including DRC, EM, IR drop, ESD, and related assessments.
• Develop and analyze floorplans, power grids, ESD structures, and bump layouts to meet electrical and performance requirements.
• Plan hierarchical floorplanning and signal routing for area, power, and performance optimization.
• Drive methodology and flow improvements to increase layout productivity and quality.
• Troubleshoot layout, tool, and flow issues and collaborate with extraction and simulation teams to debug problems.
• Collaborate with cross-functional teams to align on requirements and negotiate trade-offs.

Requirements

Must-have technical skills and experience; preferred items follow.

• Proven experience with analog device and metal layout fundamentals and mixed-signal layout techniques.
• Hands-on experience with Cadence Virtuoso layout environment and rule-based verification flows such as Calibre or ICV.
• Experience with CMOS technologies and high-voltage layout rules.
• Experience in floor planning and hierarchical layout planning for analog and mixed-signal blocks.
• Ability to perform performance verification of layouts and debug layout-related issues.
• Effective collaboration and communication skills for cross-disciplinary design reviews.

Preferred:

• Strong understanding of mismatch, parasitics, IR drop, electromigration, and their effects on circuit performance.
• Experience with common-centroid, interdigitation, symmetry layouts, and strategies to mitigate process variation.
• Experience correlating LVS, DRC, extracted parasitics (SPEF/xtract), and silicon behavior to debug issues.
• Experience optimizing layouts for noise isolation and signal integrity in mixed-signal environments.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field with 3+ years of relevant experience; or a Master's degree in a related field with 2+ years of relevant experience. Equivalent practical experience is acceptable where stated.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.