Analog IC Design Engineer, Senior Principal Engineer

Job Title

Analog IC Design Engineer, Senior Principal Engineer

Role Summary

Lead the Central Engineering AMS IP team in architecting and delivering advanced CMOS analog/mixed-signal IP (PLL, DLL, ADC, regulators, amplifiers, TX/RX, CDR, SerDes) from concept through production. Coordinate cross-functional teams to meet performance, quality, and schedule targets.

Experience Level

Senior — 10+ years of relevant analog IC design experience.

Responsibilities

Core responsibilities include hands-on analog design, technical leadership, and delivery of IP into production.

• Lead architecture and circuit implementation for PLLs, ADCs, oscillators, SerDes transmitters/receivers, and related analog blocks.
• Perform design verification and modeling using SPICE/Spectre, MATLAB, ADE and equivalent tools.
• Manage delivery of analog IP: planning, handoff to layout/verification, tapeout readiness, and support through production.
• Coordinate with layout, verification, and application teams to resolve implementation and integration issues.
• Drive system-level pre-tapeout validation and lab chip bring-up, characterization, and debugging.
• Define and meet signal integrity, noise, and low-jitter clock generation/distribution targets for multi-GHz designs.
• Mentor and lead a team of analog design engineers; provide technical direction and design reviews.

Requirements

Must-have technical skills and experience; listed concisely.

• Extensive experience with analog design and verification tools (Virtuoso, Spectre, ADE, post-layout extraction tools).
• Proven track record designing PLLs, data converters, oscillators, and high-speed SerDes (TX/RX).
• Strong knowledge of signal integrity, noise reduction, and low-jitter clocking for multi-GHz systems.
• Practical experience with FinFET analog layout considerations and high-speed design impacts.
• Experience in system-level pre-tapeout validation and lab chip bring-up/debug.
• Excellent communication and cross-functional collaboration skills.
• Nice-to-have: Experience with Single-ended High Density Parallel Interfaces, DDR5/LPDDR5, GDDR6/LPDDR6.

Education Requirements

Master's degree and/or PhD preferred in Electrical Engineering or a related technical field. The role expects significant senior-level experience (10+ years) in analog IC design.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.