Analog Design Sr. Supervisor

Role Summary

This position is focused on leading the development of accurate timing models and enhancing performance and reliability in analog mixed-signal circuit design.

Experience Level

The candidate must have 5-8 years of experience in analog/mixed signal or custom logic design.

Responsibilities

• Develop accurate timing models for macros used in multi-die designs.
• Perform analysis and verification to ensure timing models meet all performance, reliability, and design requirements.
• Collaborate closely with IP design teams to maintain high-quality timing arcs and adhere to timing methodology standards.
• Assist in timing analysis and closure for high-speed interfaces and mixed-signal IP blocks.
• Perform STA (Static Timing Analysis) using industry-standard EDA tools.
• Support constraint development and validation for timing sign-off.
• Collaborate with design, verification, and physical implementation teams to resolve timing issues.
• Utilize SiliconSmart for SPICE-based characterization and NanoTime for transistor-level Static Timing Analysis (STA).

Requirements

• BS/MS in Electronics, Electromechanics, or Telecommunications.
• Basic understanding of timing analysis, SPICE simulation, and STA concepts.
• Scripting languages: Python, TCL for automation and data processing.
• Expertise in CMOS analog design and simulation tools.
• Proficiency with Cadence Virtuoso, SNSP tools, Hspice, Spectre.
• Strong English communication skills.

Education Requirements

BS/MS in Electronics, Electromechanics, or Telecommunications.