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Analog Design Sr. Engineer

Synopsys
April 15, 2026
Full-time
On-site
Bengaluru, Karnataka, India
Level - Mid-Career

Role Summary

The Analog Design Sr. Engineer will work on designing high-performance memory interfaces including GPIO and special I/Os. This role involves collaborating with various teams to ensure design specifications and project goals are met.

Experience Level

Mid-level; 2+ years of experience in CMOS circuit design.

Responsibilities

The key responsibilities include:

  • Designing DDR/HBM Memory Interface I/O circuits.
  • Collaborating with various engineering teams to meet design specifications.
  • Executing circuit design tasks with a focus on quality and efficiency.
  • Developing analog/mixed signal circuitry using advanced CMOS technologies.
  • Contributing to the ASIC design flow from concept to implementation.
  • Providing technical insights during design reviews and troubleshooting activities.

Requirements

The following qualifications are necessary:

  • B.Tech/M.Tech degree in Electronics or Electrical Engineering.
  • 2+ years of hands-on experience in CMOS circuit design, especially deep submicron technologies.
  • Proficiency in analog/mixed signal design methodologies.
  • Familiarity with JEDEC DDR interface requirements is a plus.
  • Understanding of ESD concepts and ASIC design flow.
  • Strong written and verbal communication skills.

Education Requirements

B.Tech or M.Tech degree in Electronics or Electrical Engineering.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-04-15