Analog Design Architect - High-Speed SerDes

Role Overview

The position requires a highly proficient Architect in high-speed SerDes design with significant experience in advanced analog/mixed-signal circuits and optical I/O technologies. The individual will lead technical efforts on next-generation PHY architectures, ensuring expertise is applied from concept to production while addressing complex design challenges.

Experience Level

Senior level with a minimum of 15 years of relevant experience in analog and mixed-signal circuit design, including SerDes PHYs and high-speed I/O applications.

Responsibilities

• Define the architecture of E224+ SerDes focusing on performance, power, and latency.
• Architect high-performance analog front-ends and lead feasibility and modeling analyses of SerDes channels.
• Innovate in optical I/O integration and collaborate on long-term technology strategies across departments.
• Direct the design and optimization of analog building blocks and oversee silicon validation strategies.
• Review designs against architectural intents, collaborating across teams to achieve optimal performance.

Requirements

Qualifications include a track record in architecting multi-generation SerDes PHYs at high speeds (56G+, 112G+, 224G+), expertise in analog building blocks, and substantial hands-on experience with the silicon bring-up of high-speed designs. Proficiency in simulation tools and a comprehensive understanding of advanced process nodes is also essential.

Education Requirements

A relevant engineering degree is expected, ideally supplemented by professional certifications or advanced degrees in electrical engineering or a related field.