Analog and Mixed Signal Layout Engineer

Job Title

Analog and Mixed Signal Layout Engineer

Role Summary

Implement full-custom analog, mixed-signal and RF layouts for high-performance connectivity IPs used in AI and high-performance computing. Work from floorplanning through tapeout as part of a cross-functional engineering team focused on manufacturable, signoff-ready designs.

Collaborate closely with circuit designers, verification, CAD and technology teams to deliver robust physical implementations and improve layout methodology and automation.

Experience Level

Mid-level - guidance: 5–10 years of relevant industry experience in analog, mixed-signal, RF or custom layout development.

Responsibilities

Primary responsibilities include producing high-quality layouts, executing signoff, and driving layout automation and best practices.

• Design and implement complex analog, mixed-signal and RF layouts (floorplanning, placement, routing).
• Translate schematics into manufacturable physical designs and deliver through tapeout.
• Perform and close physical verification and signoff: DRC, LVS, ERC, antenna checks, DFM and EMIR.
• Use extraction results to optimize performance, matching, noise and reliability.
• Conduct layout reviews and establish effective layout methodologies and standards.
• Improve layout productivity via automation, scripting and AI-assisted workflows.
• Coordinate with global design, verification, CAD and technology teams and support multiple projects concurrently.

Requirements

Must-have technical skills and hands-on experience required to perform the role.

• Hands-on layout experience for SerDes, data converters, clocking, power management and transceiver building blocks.
• Proven full-custom layout and signoff experience, including RC extraction and DRC/LVS/ERC/DFM/EMIR closure.
• Proficiency with Cadence Virtuoso and industry-standard EDA tools.
• Strong understanding of semiconductor process technologies, device physics and layout-dependent effects.
• Experience applying automation, scripting or AI-assisted methods to improve layout quality and throughput.
• Demonstrated ability to deliver complex layouts to tapeout and meet project timelines in a fast-paced environment.
• Effective cross-functional communication and collaboration skills.

Nice-to-have: exposure to silicon photonics, co-packaged optics or optical transceivers; experience with advanced process nodes such as FinFET, BiCMOS or SiGe.

Education Requirements

BE/B.Tech or MS/M.Tech in Electrical/Electronics Engineering, Microelectronics, or a related field. The posting specifies 5–10 years of relevant industry experience.

About the Company

Company: Lumilens

Headquarters: San Jose, CA, USA

Lumilens develops integrated photonics and optical interconnect solutions for high-speed data communication and chip-to-chip interfaces, focusing on optical front-end hardware and co-packaged optics for advanced semiconductor systems.